1. Field of the Invention
The present invention relates to computer systems and memory system architectures, and specifically, to a method and apparatus for controlling device impedance loading in semiconductor circuits and device structures by implementing and selectively destructing novel fuse devices in the semiconductor chips.
2. Discussion of the Prior Art
Processor performance is increasingly gated by memory performance. Cache hierarchies are used to accommodate fast processors and fast memories. However, as processor speeds dramatically increase, provision of cache memories becomes increasingly insufficient, primarily due to input capacitance loading which is a major limiting factor. For example, memory chip devices are provisioned with protective devices which are used to protect the device from electrostatic discharge, for example, during device manufacture and handling. These protective devices can increase input capacitance by as much as 25%. For example, in a memory device having a common input/output terminal, a combined receiver and output driver may have a capacitance of 24 pf, with the protective device adding an additional 6 pf.
Furthermore, to enhance latency, it is necessary to reduce delay time, deleterious transmission line effects (`ringing`), loading, etc. Not only is the reduction of chip and package parasitic capacitance and inductance necessary for high performance operation, but the physical proximity between processors/memory controllers and memories is also a key to achieving reduced latency. High bandwidth (high clock rates) require terminated lines, reduced loads, etc.
It would be highly desirable to provide an apparatus and method for eliminating the protective devices of logic and memory chips/devices in the final assembly so that memory and processor performance may be enhanced without increasing electrostatic charge sensitivity of the logic or memory chip/device.
It would additionally be desirable to provide an apparatus and method for eliminating the protective devices of memory chips/chips by implementing a novel fuse structure in the protective device that may be blown after final packaging in order to eliminate loading of the protective device.
Furthermore, it would be desirable to more tightly/closely couple memory and processor chips, by providing a novel stacked memory chip/device structure that eliminates excessive capacitive and inductive loading in single and multi-processor systems in order to achieve lower latency and higher-bandwidth operation.
Finally, as prior art laser fuse devices must be blown at the wafer level prior to packaging and module burn-in, stresses may be introduced onto the chip that can promote circuit fails and performance anomalies. Laser fuses cannot be blown after circuit encapsulation and, therefore, cannot be used to correct circuit problems introduced during final module build. Thus, it would be highly desirable to provide a novel electrical fuse device, that enables circuit binning and repair to be accomplished after chip encapsulation which serves to enhance over all product yield.